1. FIELD OF THE INVENTION
The present invention relates to a telephone exchange apparatus having a means for generating a clock synchronous with a network.
2. PRIOR ART
As is well known, for example, a telephone exchange apparatus for accommodating a digital communication line normally employs a slave synchronization system so as to prevent data omission due to a difference in operating frequency between a network and the exchange apparatus. In this system, a clock is extracted from a signal received from the network, and an exchange switch is operated in synchronism with the extracted clock.
The conventional telephone exchange apparatus uses a phase controlled oscillator for generating an exchange switch operation clock synchronous with the clock extracted from a received signal. FIG. 8 shows a case wherein a DPLL is used as the conventional phase controlled oscillator.
In FIG. 8, reference numeral 30 denotes a phase comparator; 31, a counter; 32, an increment/decrement circuit; 33, a frequency-dividing counter; 34, a clock extracted from a network; 35, a phase comparison DPLL output clock; 36, a phase comparison result signal (for selecting an up- or down-counting operation of the counter 31); 37, a counter clock; 38, a counter carry-out signal; 39, a counter borrow signal; 40, a PLL reference clock; 41, an output after a clock operation of the PLL reference clock; and 42, a PLL output clock used in an operation of the exchange apparatus.
In the conventional phase controlled oscillator with the above arrangement, an operation executed when an 8-kHz frame synchronization timing clock is extracted from a network, and a clock of 32.768 MHz is used as a PLL reference clock will be described below.
As the PLL output clock 42, and the phase comparison PLL output clock 35, clocks obtained by 2.sup.n -frequency-dividing the PLL reference clock are output.
As the phase comparison PLL output clock 35, an 8-kHz clock which is the same as the clock 34 extracted from the network is output so as to compare phases with the 8-kHz clock extracted from the network. Phases are compared at each rising timing of the two clocks. As a result of comparison, if it is determined that the phase of the clock 34 extracted from the network advances from the clock 35, the value of the counter 31 is incremented by one. When the counter value has reached a preset value, one clock is inserted in the PLL reference clock 40 by the increment/decrement circuit 32. This operation is repeated until a phase difference is eliminated. Thus, the clock slaving to the operation clock of the network can be supplied to the telephone exchange apparatus.
On the other hand, as a result of comparison, if it is determined that the phase of the clock 34 extracted from the network is delayed from the clock 35, the value of the counter 31 is decremented by one. When the counter value has reached a preset value, one clock is removed from the PLL reference clock 40 by the increment/decrement circuit 32. This operation is repeated until a phase difference is eliminated. Thus, the clock slaving to the operation clock of the network can be supplied to the telephone exchange apparatus.
However, in an actual telephone exchange apparatus, it is unusual that the number of clocks extracted from the network input to the phase controlled oscillator is only one, as described above. More specifically, a plurality of digital communication lines are normally accommodated in the exchange apparatus, and when clocks can only be extracted from the accommodated digital communication lines during communications, which clock extracted from the lines is to be used as the clock extracted from the network input to the phase controlled oscillator must be controlled in accordance with the communication conditions.
FIG. 9 shows an arrangement of the conventional telephone exchange apparatus having the above-mentioned phase controlled oscillator. In FIG. 9, reference numeral 43 denotes communication lines connected to the network; 44, a line interface for interfacing with the network; 45, a network synchronization unit; 46, a central control unit; 47, an exchange switch; 48, a memory; 49, an extension interface unit; 50, telephone sets connected to the extension interface unit 49; 51, clocks extracted from the lines; 52, signals indicating line conditions; 53, an exchange switch operation clock; 54, a highway; and 55, an address bus/data bus.
FIG. 10 shows the first detailed arrangement of the conventional network synchronization unit 45.
In FIG. 10, reference numeral 56 denotes a selector; 57, a priority encoder; 58, a flip-flop; 59, a clock phase difference absorbing unit; 60, a phase controlled oscillator; 61, a switching timing generator; 65, an output frequency-divided clock; 66, a synchronization clock; and 67, an input clock to the phase controlled oscillator.
The operation of the conventional first network synchronization unit 45 will be described below with reference to FIGS. 9 and 10. In this case, a clock switching section will be mainly described.
The line interface unit 44 extracts a timing from a received signal from the network, and generates 8-kHz clocks CLK0 to CLKn by the PLL. The unit 44 outputs the clocks CLK0 to CLKn to the network synchronization unit 45. Suffixes 0 to n attached to the signal names correspond to lines from which the clocks are extracted, and in the following description, n=8. In communication state with the network, the 8-kHz clock to be output is synchronized with the timing of the network. However, in a non-communication state, a clock is generated by an independent quartz oscillator, or the like, and is not always synchronized with the timing of the network.
The line interface unit 44 outputs signals COM0 to COMn indicating line conditions to the network synchronization unit 45. The line interface unit 44 outputs, as the signals COM0 to COMn, signals at logic "0" in a communication state, and signals at logic "1" in a non-communication state. Note that suffixes 0 to n added to the signal names represent line numbers, and in the following description, n=8.
The line condition signals COM0 to COM8 are input to the priority encoder 57 (FIG. 10) of the network synchronization unit 45. The priority encoder 57 converts the smallest line number of those of the lines at logic "0" into 3-bit binary data, and outputs the binary data to the flip-flop 58.
For example, when the signals COM2, COMS, and COM8 are at logic "0", 3-bit data "010" is output
When all the line condition signals are at logic "1" i e when no communications are performed at all, 3-bit data "000" is output. In this case, the clock CLK0 is selected and output. The clock CLK0 is a clock of a predetermined line number "0" and the clock extracted from this line is selected.
The output from the priority encoder 57 is temporarily latched by the flip-flop 58, and is then input to the selector 56 having an 8-bit input. The selector 56 selects a clock to be output to the phase controlled oscillator 60 from the eight 8-kHz clocks 51 supplied from the line interface unit 44. For example, when the signals COM2, COM5, and COMB are at logic "0", since the output from the priority encoder is 3-bit data "010" the clock CLK2 is selected
When the second line 2 starts a communication, the signal COM2 goes to logic "1", and the output from the priority encoder 57 is changed to 3-bit data "101". The selector 56 selects the clock CLK5 according to the output from the encoder 57, and the clock CLK5 is input to the phase controlled oscillator 60.
When the conventional clock phase difference absorbing unit 59 outputs the clock signal 63 input from the selector 56 to the phase controlled oscillator 60, it merely outputs it in synchronism with the synchronization clock signal 66 from the phase controlled oscillator 60, and can merely absorb a phase difference from the internal clock of the phase controlled oscillator 60.
With the above-mentioned operations, a switching operation is performed, so that a clock extracted from the line in communication can be input to the phase controlled oscillator 60.
FIG. 11 shows the second detailed arrangement of the conventional network synchronization unit 45. Note that other arrangements are the same as those shown in FIG. 9.
In FIG. 11, reference numeral 70 denotes a clock phase difference absorbing unit, which has delay circuits corresponding to input clocks. Reference numeral 71 denotes a flip-flop; 72, a selector; 73, a phase controlled oscillator; and 74, a switching timing generator. Reference numeral 75 denotes a selector control signal; 76, a selected extracted clock; 77, a switching timing signal; 78, a switching timing generator output and 79, an output frequency-divided clock.
The operation of the conventional second network synchronization unit 45 will be described below with reference to FIGS. 9 and 11. In this case, a clock switching section will be mainly described.
The operation of the line interface unit 44 is the same as that described above. 8-kHz clocks output from the line interface unit 44 are input to the phase difference absorbing unit 70 shown in FIG. 11. The outputs from the phase difference absorbing unit 70 are input to the selector 72, and are switched by the selector 72 in accordance with the selector control signal (clock switching control signal 75) from the flip-flop 71 which latches the signals 52 (COM0 to COMn) output from the line interface unit 44 and indicating line conditions (communication conditions).
The clock phase difference absorbing unit 70 is a circuit for eliminating the influence of a phase difference among clocks extracted from the lines. The timings of the respective lines have phase differences due to delay time differences in respective line transmission paths. For this reason, the respective clocks are optimally delayed, so that phases of the clocks input to the phase controlled oscillator 73 are locked, thereby preventing a phase difference before and after a clock switching operation.
However, the first prior art suffers from the following drawbacks since the means such as the priority encoder 57, the selector 56, and the like are used as means for switching clock signals to be input to the phase controlled oscillator 60.
(1) In order to obtain a stable output from the phase controlled oscillator 60, it is preferable that a clock input to the phase controlled oscillator 60 is also stable. For this purpose, the switching frequency of clocks is preferably as small as possible.
In the conventional arrangement, however, even when a given line maintains a communication state for a long period of time, if a line having a smaller number than the given line starts or ends a communication, the clock is unconditionally switched, and a stable clock cannot be input.
(2) When all the lines are in a non-communication state, a clock from a predetermined line is selected. the lines must be accommodated in turn from a predetermined line position in a predetermined order. For this reason, it is troublesome to connect lines to the exchange apparatus, and a connection error may OCCUr.
In the second prior art, since all the clocks extracted from the lines are input to the phase difference absorbing unit 70, delay circuits corresponding in number to the lines are undesirably required.
In particular, this poses a serious problem in a telephone exchange apparatus which accommodates a large number of lines.